Advanced Electronic Technology Center We believe in Converting Dreams to Reality

Sai Rahul Chalamalasetti

Sai Rahul Chalamalasetti is a graduate student at University of Massachusetts Lowell ,where he is pursuing the Master's degree in Computer Engineering under the supervision of Prof.Martin Margala. His research interests involves power efficient/High throughput reconfigurable architectures. He also works on implementation of adaptable architectures and signal processing applications on FPGA's.

 

 
Education
M.S.E.E. University of Massachusetts, Lowell, 2009
Ph.D. University of Massachusetts, Lowell, 2012
Publications:
Book Chapters

1. Wim Vanderbauwhede, Sai Rahul Chalamalasetti, Martin Margala, “MORA: High-Level FPGA Programming Using a Many-core Framework,” Chapter in, “Multicore Technology: Architecture, Reconfiguration, and Modeling”, edited by Muhammad Yasir Qadir, Steve J Sangwine, CRC Press publishers, will appear in 2012.
2. Sohan Purohit, Sai Rahul Chalamalasetti, Martin Margala, “Low Overhead Radiation Hardening Techniques for Embedded Architectures”, Chapter in, “Embedded Systems: Hardware Design and Implementations,” edited by Kris Iniewski, John Wiley & Sons publishers, will appear in 2012

 

Journal Publications

1. Sohan Purohit, Sai Rahul Chalamalasetti, Martin Margala, Matt Roy, Wim Vanderbauwhede, ”Design and Evaluation of High Performance Reconfigurable Processing Elements”, under Review, IEEE Transactions on Very Large Scale Integration (VLSI) Systems
2. Sohan Purohit, Sai Rahul Chalamalasetti, Martin Margala, Wim Vanderbauwhede, ”Throughput/Resource Efficient Reconfigurable Processor for Multimedia Processing”, revision submitted, IEEE Transactions on Very Large Scale Integration (VLSI) Systems
3. Wim Vanderbauwhede, Sai Rahul Chalamalasetti, Martin Margala, “Throughput Analysis for a High-Performance FPGA-Accelerated Real-time Search Application,” International Journal of Reconfigurable Computing, vol. 2012, Article ID 507173, 16 pages, 2012
4. Sai Rahul Chalamalasetti, Sohan Purohit, Martin Margala, Wim Vanderbauwhede, “Radiation Hardened Reconfigurable Array with Instruction Roll-Back,” Embedded Systems Letters, IEEE, vol.2, no.4, pp.123-126, Dec. 2010

Conference Publications

1. Sai Rahul Chalamalasetti, Martin Margala, Wim Vanderbauwhede, Mitch Wright, Parthasarathy Ranganathan, “Evaluating FPGA-acceleration for Real-time Unstructured Search, ” accepted, 11th International Symposium on Performance Analysis of Systems and Software, April 1-3 2012, New Brunswick, NJ, USA
2. Wim Vanderbauwhede, Sai Rahul Chalamalasetti, Sohan Purohit, Martin Margala, “A few lines of code, thousands of cores: High-level FPGA programming using vector processor networks,” In Proceedings of 9th International Conference on High Performance Computing and Simulation(HPCS 2011), pp. 461-467, July 4-8 2011, Istanbul, Turkey
3. Wim Vanderbauwhede, Martin Margala, Sai Rahul Chalamalasetti, Sohan Purohit, “A C++-embedded DSL for programming the MORA soft processor array,” In Proceedings of 21st IEEE/ACM/IFIP International Conference on Application Specific Processors, Architectures and Applications (ASAP 2010), pp. 141-148, July 7-9 2010, Rennes, France
4. Sohan Purohit, Sai Rahul Chalamalasetti, Martin Margala, “Low Overhead Soft Error Detection and Correction Scheme for Reconfigurable Pipelined Data Paths,” In Proceedings of 5th NASA/ESA Conference on Adaptive Hardware Systems (AHS 2010), pp. 59-65, June 15-18 2010, Anaheim California, USA
5. Sohan Purohit, Sai Rahul Chalamalasetti, Martin Margala, “Design of Self Correcting Radiation Hardened Digital Circuits using Decoupled Ground Bus,” In Proceedings of the 20th Symposium on Great Lakes Symposium on VLSI (Providence, Rhode Island, USA, May 16 - 18, 2010). GLSVLSI '10. ACM, New York, NY, 405-408
6. Sai Rahul Chalamalasetti, Wim Vanderbauwhede, Sohan Purohit, Martin Margala, “A Low Cost Reconfigurable Soft Processor for Multimedia Applications: Design Synthesis and Programming Model,” Field Programmable Logic and Applications, 2009. FPL 2009. International Conference on , vol., no., pp.534-538, Aug. 31 2009-Sept. 2 2009
7. Wim Vanderbauwhede, Martin Margala, Sai Rahul Chalamalasetti, Sohan Purohit, “Programming Model and Low-level Language for a Coarse-grained Reconfigurable Multimedia Processor,” published in The International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA’2009)
8. Sai Rahul Chalamalasetti, Sohan Purohit, Martin Margala, Wim Vanderbauwhede, “MORA - An Architecture and Programming Model for a Resource Efficient Coarse Grained Reconfigurable Processor,” Adaptive Hardware and Systems, 2009. AHS 2009. NASA/ESA Conference on , vol., no., pp. 389-396, July 29, 2009-Aug. 1, 2009
9. Sohan Purohit, Sai Rahul Chalamalasetti, Martin Margala, “A 1.2V, 1.02 GHz 8 bit SIMD Compatible Highly Parallel ALU for Multi-precision Arithmetic,” In Proceedings of the 19th ACM Great Lakes Symposium on VLSI (Boston Area, MA, USA, May 10 - 12, 2009). GLSVLSI '09. ACM, New York, NY, 433-436
10. Sohan Purohit, Sai Rahul Chalamalasetti, Martin Margala, Pasquale Corsonello, “Power-efficient High Throughput Reconfigurable Datapath Design for Portable Multimedia Devices,” Reconfigurable Computing and FPGAs, 2008. ReConFig '08. International Conference on Reconfigurable computing and FPGAs , vol., no., pp .217-222, Dec. 3-5, 2008
11. Sohan Purohit, Sai Rahul Chalamalasetti, Martin Margala, Pasquale Corsonello, “Power/throughput/area efficient PIM-based reconfigurable array for parallel processing,” SOC Conference, 2008 IEEE International SOC Conference , vol., no., pp. 375-378, Sept. 17-20, 2008

Workshop Papers

1. Jonathan LaBroad, Yan Luo, Sai Rahul Chalamalasetti, Timothy Ficarra, Martin Margala, “Reconfigurable Logic Accelerated Heterogeneous Multicore Architecture for Dynamic Workloads,” 2nd Workshop on SoC Architecture, Accelerators and Workloads, SAW-2, Feb 12, 2011, San Antonio, Texas, USA
2. Sohan Purohit, Sai Rahul Chalamalasetti, Martin Margala, “Low Overhead Soft Error Detection and Correction Scheme for High Performance Pipelined Data paths,” 2010 IEEE North Atlantic Test Workshop, May 12-14, 2010, Fishkill, New York, USA
 
  •  
Contact
1 University Ave, Lowell MA -01854
Tel:- 978-934-3310, 978-934-3827, 978-934-2986
 
 
 
Legal
AETC Lab © 2012 All Rights Reserved